The present invention relates to electronic circuits, and more particularly, to digitally controlled delay-locked loop circuits.
Digital delay-locked loop circuits typically maintain a phase relationship between an input reference clock signal and a feedback clock signal. Many digital delay-locked loops generate a significant phase error between the feedback clock signal and the input reference clock signal. In addition, many digital delay locked loops generate an undesirable amount of jitter in the feedback clock signal.
Therefore, it would be desirable to provide a digital delay-lock loop that can generate a clock signal having reduced jitter and a reduced phase error relative to an input reference clock signal.